For clock clean-up applications such as these, narrow (<1 kHz) low-pass filter bandwidths are recommended. Such a PLL is called a clock clean-up PLL. When the output frequency is equal to the input frequency it creates one of the simplest PLL configurations. All the in-band noise contributed by the PLL reference and PFD circuitry is filtered out by the low-pass filter, leaving only the much lower VCXO noise (Figure 7) outside the loop bandwidth (Figure 8). Total PLL noise.Īs can be seen with the ADIsimPLL plots shown, the noisy phase noise profile of the REF IN (Figure 6) is filtered by the low-pass filter.
SWITCHING SPEED OF A PROCSSOR FREE
Returning to our original example of the noisy clock that requires cleaning, the phase noise profile of the clock, free running VCXO, and closed-loop PLL can be modeled in ADIsimPLL. Phase frequency detector, frequency, and phase lock. If the frequency to –IN is higher than +IN, the reverse happens. In this way, the –IN frequency will increase as the VCO increases, and the two PFD inputs will eventually converge or lock to the same frequency (Figure 5). Using this architecture, the input to +IN below is at a higher frequency than the –IN (Figure 4), and the resultant charge pump output is pumping current high, which, when integrated in the PLL low-pass filter, will push the tuning voltage of the VCO up. For more details on PFD operation, consult “ Phase-Locked Loops for High Frequency Receivers and Transmitters.”
These current sources are known as the charge pump. One Q output enables a positive current source, and the other Q output enables a negative current source. It uses two D-type flip flops with a delay element. The phase frequency detector in Figure 3 compares the input to F REF at +IN and the feedback signal at –IN. As such, it can be used with a high quality voltage controlled crystal oscillator (VCXO) and a narrow low-pass filter to clean up a noisy REF IN clock. The ADF4002 is a PLL that can be configured as a standalone PFD (with the feedback divider N = 1). The PFD compares the frequency and phase of the input to REF IN to the frequency and phase of the feedback to RF IN. The first essential element in this circuit is the phase frequency detector (PFD). For the purposes of this article we shall only consider a classical digital PLL architecture as implemented on the Analog Devices ADF4xxx family of PLLs.
When the comparison is in steady-state, and the output frequency and phase are matched to the incoming frequency and phase of the error detector, we say that the PLL is locked. In Figure 2 there is a negative feedback control loop operating in the frequency domain.
In its most basic configuration, a phase-locked loop compares the phase of a reference signal (F REF) to the phase of an adjustable feedback signal (RF IN) F 0, as seen in Figure 1. Basic Configuration: Clock Clean-Up Circuit The article references the Analog Devices ADF4xxx and HMCxxx family of PLLs and voltage controlled oscillators (VCOs), and uses ADIsimPLL (Analog Devices in-house PLL circuit simulator) to demonstrate these different circuit performance parameters. This article explains some of the building blocks of phase locked loop circuits with references to each of these applications, in turn, to help guide the novice and phase locked loop expert alike in navigating part selection and the trade-offs inherent for each different application. Phase-locked loop (PLL) circuits exist in a wide variety of high frequency applications, from simple clock clean-up circuits, to local oscillators (LOs) for high performance radio communication links, and ultrafast switching frequency synthesizers in vector network analyzers (VNA).
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